1. Field of the Invention
The invention relates to frequency synthesis employing a phase locked loop and more particularly to techniques for modulating a phase locked loop frequency synthesizer.
2. Description of the Related Art
Conventional communication transmitters traditionally employ a phase locked loop (PLL) synthesizer for frequency synthesis of a communication signal modulated with transmission data. The PLL frequency synthesizer provides precise control of the frequency of the communication signal and accordingly enables the transmission data to be reliably transmitted at a stable, known frequency.
Recently, Σ-Δ modulators are used in PLL frequency synthesizers to control the division factor of a multi-modulus divider. Phase locked loop frequency synthesis is a well-known technique to generate one of many related signals from a frequency variable voltage controlled oscillator (VCO). In a PLL, an output signal from the VCO is coupled to a programmable frequency divider which divides the output signal by a selected integer to generate a frequency divided signal supplied to a phase detector. The phase detector compares the frequency divided signal to a reference signal from another fixed frequency oscillator often selected for stability of frequency over time and environmental changes. Any difference in phase between the frequency divided signal and the reference signal is output from the phase detector, coupled through a loop filter, and applied to the VCO such that the output signal from the VCO changes in frequency, minimizing phase error between the frequency divided signal and the reference signal. With a constant division factor, the output frequency step size is kept equal with the reference signal frequency. With the PLL, an engineering compromise must be struck between the competing requirements of loop lock time, output frequency step size, noise performance and spurious signal generation.
To overcome the limitations of the PLL, programmable frequency dividers capable of effectively dividing by non-integers have been developed. Output frequency step sizes which are fractions of the reference signal frequency are obtained while maintaining a high reference frequency and wide loop bandwidth. The synthesizers are known as fractional-N frequency synthesizers.
Furthermore, an Σ-Δ modulator can be used to control the frequency divider of the phase locked loop. Characteristics of an Σ-Δ modulator are such that the quantization noise at its output tends to be toward the high end of the spectrum. The Σ-Δ modulator is a quantizer that uses feedback to reduce the quantization noise in a limited frequency band. For this application, the Σ-Δ modulator preferably has low quantization noise within the bandwidth of the modulation. The Σ-Δ modulator may be any type of Σ-Δ modulator, such as those described in Steven R. Northsworthy, Richard Schrier and Gabor Temes, Delta-Sigma Data Converters. Theory, Design and Simulation, IEEE Press 1997.
FIG. 1 is a block diagram of an Σ-Δ modulator controlled PLL frequency synthesizer 100. As shown, the phase locked loop frequency synthesizer 100 comprises a phase locked loop 110, a modulation processor 120, and a frequency regenerator 130. A periodic reference signal SR is fed to a phase detector 101 together with a feedback signal SF output by a multiple-modulus frequency divider (MMD) 105. The output of the phase detector 101 is a pulse related to the phase difference between the reference signal SR and the feedback signal SF. The output of the phase detector 202 is filtered through a loop filter 102 and fed to a voltage controlled oscillator (VCO) 103. Due to the feedback in the phase locked loop, the frequency of a first output modulation signal SOM1 output by the VCO 103 is driven to equal the frequency of the reference signal SR multiplied by the division factor of the frequency divider 105. Hence, the frequency of the first output modulation signal SOM1 can be controlled by controlling the division factor. In the Σ-Δ modulator 106 controlled PLL frequency synthesizer 100, the division factors are generated using an Σ-Δ modulator 106. The division factor of the frequency divider 105 can be changed once every frequency period of the reference signal SR. Channel selection can be performed by adding in an adder 108 an offset signal SOFF to the input of the Σ-Δ modulator 106. The output of the Σ-Δ modulator 106 is then used to control the division factor in the frequency divider.
A modulation processor 120 generates, based on an input modulation signal SIM, the input to the Σ-Δ modulator 106. The modulation processor 120 conventionally comprises a waveform generator 121 for pulse shaping and a PLL compensator for compensation of distortion induced by the PLL 110. Various modulation compensation circuits can compensate for distortion induced by the PLL 100 and enable wider bandwidth PLL modulation. For example, Perrott et al., in U.S. Pat. No. 6,008,703, disclose a PLL comprising a frequency response comprising a characteristic cutoff frequency, a modulation data receiver for receiving from a modulation source digital input modulation data comprising a bandwidth that exceeds the cutoff frequency, and a digital processor for digitally processing the input modulation data to amplify modulation data at frequencies higher than the phase locked loop cutoff frequency; and Eriksson et al. in U.S. Pat. No. 6,011,815, disclose pre-filtering for mitigating the distortion of the PLL.
The first output modulation signal SMO1 generated by the PLL 110 is further provided to the frequency regenerator 130. The frequency regenerator 130 is implemented to generate a second output modulation signal SOM2 for transmission and with a frequency range not overlapping the output frequency range of the VCO 103 to prevent the VCO 130 from being pulled or interfered by circuits such as a power amplifier following the PLL frequency synthesizer 100. Typically, the frequency regenerator 130 is implemented as a frequency divider or a frequency multiplier, and/or frequency mixers.
Although the frequency regenerator 130 in the conventional PLL frequency synthesizer 100 solves pulling and interference issues, distortion, noise, and timing errors can be generated. More specifically, compared to the output directly provided by the VCO in a PLL frequency synthesizer without the implementation of frequency regenerator, the modulation index of the second output modulation signal SOM2 in the PLL 100 is distorted, and both the noise and timing phase errors of the second output modulation signal SOM2 n the PLL frequency synthesizer 100 are greater. As a result, decreased performance criteria of transmission specifications may occur.